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november 1999 1 copyright ? 1998, 1999 by lsi logic corporation. all rights reserved. CW001007 arm7tdmi microprocessor core datasheet the lsi logic CW001007 core is an implementation of the advanced risc machines arm7tdmi 32-bit risc microprocessor developed by advanced risc machines. the cw1007 meets the requirements of the lsi logic coreware a methodology and is implemented using lsi logic g11? 0.25-micron process technology. the g11-p 2.5 v core supports speeds up to 80 mhz. the g11-v 1.8 v core supports speeds up to 55 mhz (under worst case commercial conditions) and consumes less than 1 mw per mhz. the core area is just under 2.5 mm 2 . with its high performance, low power requirements, and small size,the arm7tdmi core is ideal for a wide variety of embedded applications. figure 1 core block diagram scan chain 0 a[31:0] core scan chain 1 d[31:0] nopc nrw all other signals tck tms tdi ntrst tdo ntrans nmreq scan chain 2 icebreaker tap controller mas[1:0] bus splitter din[31:0] dout[31:0] tapsm[3:0] ir[3:0] screg[3:0] extern1 extern0 rangeout1 rangeout0
2 CW001007 arm7tdmi microprocessor core the CW001007 core employs an innovative architectural strategy known as thumb , which can execute both 32-bit and 16-bit instructions to support high volume applications with memory restrictions and applications where code density is an issue. because it employs both the arm ? and thumb instruction sets, it allows a wide choice of development tools and third-party rtoss (real-time operating systems) created and supported by arm and a host of third-party vendors. see thumb architecture, on page 7 for more information. the arm architecture is based on reduced instruction set computer (risc) principles, so the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers (cisc). this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. the arm memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. speed critical control signals are pipelined to exploit the fast local access modes offered by industry-standard dynamic rams.
CW001007 arm7tdmi microprocessor core 3 features and bene?ts description figure 1 shows a block diagram of the CW001007 core. the CW001007 core consists of four major blocks: icebreaker, tap (test access port ) controller, bus splitter, and the microprocessor (shown in more detail in figure 2 ). the icebreaker module provides integrated debugging support for the internal core module. it consists of two real-time watchpoint units, a control register, and a status register. lsi logic 0.25 micron g11 technology a choice of g11-p for high performance applications or g11-v for low power applications access to full coreware library high density and a small die size increase the area available for integration of other logic rtl design approach simpli?ed process migration simpli?ed cpu customization complete and accurate timing model arm 32-bit risc execution engine delivers up to 80 mhz compatibility with a wide range of parts from other vendors supported by an existing array of arm development tools and rtoss extensive set of peripherals designed to the amba standard simpli?es system development facilities design reuse and customization built-in code decompression (thumb) reduces total system memory requirements includes full scan test structures very high fault coverage for manufacturing test includes arm icebreaker debugger ideal for deeply embedded asics
4 CW001007 arm7tdmi microprocessor core the tap controller module controls three jtag scan chains used for testing, debugging, and programming the icebreaker. a fourth scan chain is also provided for an external boundary chain around the pads of a packaged device. the bus splitter is used to split the internal bidirectional data bus into three unidirectional buses for asic designs that prohibit bidirectional data buses. the microprocessor module provides the main functionality of the microprocessor core. figure 2 shows the microprocessor module in more detail.
CW001007 arm7tdmi microprocessor core 5 figure 2 microprocessor module block diagram nreset nmreq seq abort nirq nfiq nrw lock ncpi cpa cpb nwait mclk nopc ntrans instruction decoder and control logic instruction pipeline and read data register dbe d[31:0] 32-bit alu barrel shifter address incrementer address register register bank (31 x 32-bit registers) (6 status registers) a[31:0] ale multiplier abe write data register nm[4:0] 32 x 8 nenout nenin tbe scan control breakpti dbgrqi nexec dbgack eclk isync ape bl[3:0] mas[1:0] tbit highz and thumb instruction decoder incrementer bus alu bus a bus pc bus b bus
6 CW001007 arm7tdmi microprocessor core pipelining a three-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. building blocks to facilitate system design, lsi logic offers a complete library of peripherals implemented around the popular amba open bus standard. these peripherals can be used as-is, or modi?ed to suit the speci?c application. figure 3 shows a typical amba system that incorporates the arm7tdmi core. figure 3 a typical amba system debug and full scan the arm7tdmi core uses full scan methodology for high fault coverage and contains the arm icebreaker module for effective debugging, even in the most deeply embedded asics. as part of the lsi logic coreware library, the arm7tdmi core is supported by lsi logic asic design methodology, tools, and expert technical support. arm processor on-chip ram external bus interface uart timer pio b r i d g e advanced system bus high performance high bandwidth advanced peripheral bus low power simple interface
CW001007 arm7tdmi microprocessor core 7 thumb architecture the CW001007 processor has two instruction sets: standard 32-bit arm set a 16-bit thumb set the thumb set is a super-reduced instruction set. its 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65% of the code size of arm and 160% of the performance of an equivalent arm processor connected to a 16-bit memory system. thumb instructions operate with the standard arm register con?guration, allowing excellent interoperability between arm and thumb states. each 16-bit thumb instruction has a corresponding 32-bit arm instruction with the same effect on the processor model. the major advantage of a 32-bit (arm) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions and to address a large address space ef?ciently. when processing 32-bit data, a 16-bit architecture will take at least two instructions to perform the same task as a single arm instruction. however, not all the code in a program will process 32-bit data (for example, code that performs character string handling), and some instructions, like branch instructions, do not process any data at all. if a 16-bit architecture only has 16-bit instructions, and a 32-bit architecture only has 32-bit instructions, then overall the 16-bit architecture will have better code density and better than one half the performance of the 32-bit architecture. clearly 32-bit performance comes at the cost of code density. thumb breaks this constraint by implementing a 16-bit instruction length on a 32-bit architecture, making the processing of 32-bit data ef?cient with a compact instruction coding. this provides far better performance than a 16-bit architecture, with better code density than a 32-bit architecture.
8 CW001007 arm7tdmi microprocessor core thumb also has a major advantage over other 32-bit architectures with 16-bit instructions. this is the ability to switch back to full arm code and execute at full speed. this enables critical loops for applications such as fast interrupts and dsp algorithms to be coded using the full arm instruction set and linked with thumb code. the overhead of switching from thumb code to arm code is folded into subroutine entry time. various portions of a system can be optimized for speed or for code density by switching between thumb and arm execution as appropriate.
CW001007 arm7tdmi microprocessor core 9 instruction set summary the CW001007 has two instruction setsa standard 32-bit arm set, and a 16-bit thumb set. ta b l e 1 summarizes the arm instruction set, and ta b l e 2 summarizes the thumb set. table 1 arm instruction set (32-bit) op description branch instructions b branch bl branch with link bx branch and exchange data processing instructions adc add with carry add add and logical and bic bit clear cmn compare negated cmp compare eor logical exclusive or mov move mvn move not orr logical (inclusive) or rsb reverse subtract rsc reverse subtract with carry sbc subtract with carry sub subtract teq test equivalence tst test multiply instructions mla multiply accumulate mul multiply mlal multiply accumulate long mull multiply long program status register (psr) transfer instructions mrs move psr status/flags to register msr move register to psr status/flags load and store instructions ldx load multiple registers, byte, word, halfword stx store multiple registers, byte, word, halfword semaphore instructions swpx swap word/byte between register and memory coprocessor instructions cdp coprocessor data processing ldc load coprocessor from memory mcr move to coprocessor register from arm mrc move to arm register from coprocessor stc store coprocessor register to memory interrupt instructions swi software interrupt table 2 thumb instruction set (16-bit) op description branch instructions b branch bl branch with link bx branch and exchange data processing instructions adc add with carry add add and logical and asr arithmetic shift right bic bit clear cmn compare negative cmp compare eor exclusive or lsl logical shift left lsr logical shift right mov move mvn move not neg negate orr logical or ror rotate right sbc subtract with carry sub subtract tst test bits multiply instructions mul multiply load and store instructions ldx load multiple registers, byte, word, halfword pop pop registers push push registers stx store multiple registers, byte, word, halfword interrupt instructions swi software interrupt
10 CW001007 arm7tdmi microprocessor core differences from cw001004 this implementation of the arm7tdmi differs from the previous lsi logic implementation (cw001004) in the way in which the jtag idcode register is implemented. in the cw001004, the jtag idcode register returned a 32-bit device identi?cation code in a format de?ned by arm ltd. in CW001007, the register returns a value of 0 (indicating "no valid id present"). it is possible to use the jtag state signals that are outputs from the CW001007 to implement an idcode register external to the CW001007 core. signal descriptions the CW001007 signals are shown in figure 4 , and are listed by functional group: clocks interrupts bus controls debug scan test boundary scan boundary scan control processor interface memory interface memory management interface coprocessor interface in the descriptions that follow, the verb assert means to drive true or active. the verb deassert means to drive false or inactive.
CW001007 arm7tdmi microprocessor core 11 figure 4 arm7tdmi logic diagram nreset nmreq seq abort nirq nfiq nrw lock ncpi cpa cpb nwait mclk nopc ntrans instruction decoder and control logic instruction pipeline and read data register dbe d[31:0] 32-bit alu barrel shifter address incrementer address register register bank (31 x 32-bit registers) (6 status registers) a[31:0] ale multiplier abe write data register nm[4:0] 32 x 8 nenout nenin tbe scan control breakpti dbgrqi nexec dbgack eclk isync ape bl[3:0] mas[1:0] tbit highz and thumb instruction decoder incrementer bus alu bus a bus pc bus b bus
12 CW001007 arm7tdmi microprocessor core clocks mclk memory clock input input this clock controls the timing of all CW001007 memory accesses and internal operations. nwait not wait input deasserting this signal makes the core wait for an integer number of mclk cycles. eclk external clock output output in normal operation, this is mclk exported from the core. when the core is being debugged, this is dclk. interrupts nfiq not fast interrupt request input an interrupt request that causes the processor to be interrupted if taken low. nirq not interrupt request input this is the same as nfiq, but with lower priority. isync synchronous interrupts input when low, this signal indicates that interrupt request inputs are to be synchronized by the arm core. bus controls nreset not reset input a low level causes the instruction being executed to terminate abnormally. when high for at least one clock cycle, the processor restarts from address 0. busen data bus con?guration input determines whether the bidirectional data bus or the unidirectional data buses are to be used. highz high z instruction output this signal denotes that the highz instruction has been loaded into the tap controller. bigend big endian con?guration input when this signal is high the processor treats bytes in memory as being in big endian format.
CW001007 arm7tdmi microprocessor core 13 nenin not enable input input used with nenout to control the data bus during write cycles. nenout not enable output output during a data write cycle, this signal is driven low during phase 1, and remains low for the entire cycle. nenouti not enable output output used to aid arbitration in shared bus systems. abe address bus enable input when low, puts the address bus drivers into a high impedance state. ape address pipeline enable input when high, this signal enables the address timing pipeline. ale address latch enable input used to control transparent latches on the address outputs. dbe data bus enable input when driven low, puts the data bus into the high impedance state. tbe test bus enable input when low, puts the data bus, the address bus, lock, mas[1:0], nrw, ntrans, and nopc into a high impedance state. busdis bus disable output used to disable external logic driving onto the bidirectional data bus during scan testing. ecapclk extest capture clock output removes the need for external logic to enable the internal 3-state bus during scan testing. debug dbgrq debug request input when high causes the core to enter debug state after executing the current instruction.
14 CW001007 arm7tdmi microprocessor core breakpt breakpoint input when high, causes the current memory access to be breakpointed. dbgack debug acknowledge output when high, indicates that the core is in debug state. nexec not executed output when high, indicates that the instruction in the execution unit is not being executed. extern0 external input 0 input input to icebreaker logic that allows breakpoints and/or watchpoints to be dependent on an external condition. extern1 external input 1 input input to icebreaker logic that allows breakpoints and/or watchpoints to be dependent on an external condition. dbgen debug enable input disables the debug features of the core. rangeout0 icebreaker rangeout 0 output indicates that the icebreaker watchpoint register 0 has matched the conditions currently present on the address, data and control buses. rangeout1 icebreaker rangeout 1 output this signal is the same as rangeout0 but corresponds to the icebreaker watchpoint register 1. dbgrqi internal debug request output represents the debug request signal that is presented to the processor. commrx communications channel receive output when high, denotes that the communications channel receive buffer is empty. commtx communications channel transmit output when high, denotes that the communications channel transmit buffer is empty. scan test fullscan master scan mode select input enables full scan input.
CW001007 arm7tdmi microprocessor core 15 ramtest ramtest scan mode select input places the core in ramtest mode, if fullscan is asserted. ramtest_in ramtest scan chain input input scan input for the core memory scan chain in ramtest. ramtest_out ramtest scan chain output output scan output for the core memory scan chain in ramtest mode. scan_en global scan enable input enables serial loading of the scan registers through the scan chain in production test or ramtest mode. scan_in full scan chain input input scan input for core memory scan chain in production test mode. scan_out full scan chain output output scan output for the core memory scan chain in production test mode. wenctest ramtest write enable input controls core memory writes in ramtest mode. boundary scan tck test clock input the clock used for test operations. tck1 tck, phase 1 output this clock represents phase 1 of tck. tck2 tck, phase 2 output this clock represents phase 2 of tck. tms test mode select input selects the test mode. tdi test data input input this signal is for test data input. tdo test data output output output from the boundary scan logic.
16 CW001007 arm7tdmi microprocessor core ntrst not test reset input active low reset signal for the boundary scan logic. tapsm[3:0] tap controller state machine output shows the current state of the tap controller state machine. ir[3:0] tap controller instruction register output shows the current instruction loaded into the tap controller instruction register. ntdoen not tdo enable output when low, this signal denotes that serial data is being driven out on the tdo output. screg[3:0] scan chain register output shows the id number of the scan chain currently selected by the tap controller. boundary scan control drivebs boundary scan cell enable output controls the multiplexers in the scan cells of an external boundary scan chain. ecapclkbs extest capture clock for boundary scan output clock used to capture the core outputs during extest. icapclkb sintest capture clock output clock used to capture the core outputs during intest. nhighz not highz output places the scan cells of a scan chain in the high impedance state. pclkbs boundary scan update clock output used by an external boundary scan chain as the update clock. rstclkbs boundary scan reset clock output denotes that either the tap controller state machine is in the reset state or that ntrst has been asserted. sdinbs boundary scan serial input data output the serial data to be applied to an external scan chain.
CW001007 arm7tdmi microprocessor core 17 sdoutbs boundary scan serial output data input the serial data out of the boundary scan chain. shclkbs boundary scan shift clock, phase 1 output used to clock the master element of the scan cells. shclk2bs boundary scan shift clock, phase 2 output used to clock the slave element of the scan cells. processor interface nm[4:0] not processor mode output output signals that are the inverse of the internal status bits indicating the processor operation mode. tbit thumb instruction set enable output when high, denotes that the processor is executing the thumb instruction set. when low, the processor is executing the arm instruction set. memory interface a[31:0] addresses output this is the processor address bus. d[31:0] data bus bidirectional bidirectional bus for data transfers between the processor and external memory. dout[31:0] data output bus output this is the data out bus, used to transfer data from the processor to the memory system. din[31:0] data input bus input the input data bus used to transfer instructions and data between the processor and memory. nmreq not memory request output when low, this signal indicates that the processor requires memory access during the following cycle. seq sequential address output becomes high when the address of the next memory cycle is related to that of the last memory access.
18 CW001007 arm7tdmi microprocessor core nrw not read/write output when high, indicates a processor write cycle; when low, a read cycle. mas[1:0] memory access size output indicates to the external memory system whether a word, halfword, or byte length transfer is required. bl[3:0] byte latch control input these signals control when data and instructions are latched from the external data bus. lock locked operation output when lock is high, the processor is performing a locked memory access. memory management interface ntrans not memory translate output when this signal is low it indicates that the processor is in user mode. abort memory abort input allows the memory system to tell the processor that a requested access is not allowed. nopc not op-code fetch output when low, indicates that the processor is fetching an instruction from memory. coprocessor interface ncpi not coprocessor instruction output this output is taken low when the core starts to execute a coprocessor instruction. cpa coprocessor absent input a coprocessor that is capable of performing the operation that CW001007 is requesting should take cpa low immediately. cpb coprocessor busy input a coprocessor that is capable of performing the requested operation, but cannot commit to starting it immediately, should indicate this by driving cpb high.
CW001007 arm7tdmi microprocessor core 19 speci?cations this section speci?es the CW001007 architectures electrical and mechanical characteristics. the timing parameters given here are preliminary data and subject to change. ac timing output load is 0.24 pf. in the two tables that follow the letters after the signal name refer to: rising edge (r) and falling edge (f). values are given for two operating conditions in worst-case process: table3:tj=125 c, 2.5 v - 5% table4:tj=125 c, 1.8 v - 5% table 3 ac parameters - tj = 125 c, 2.5 v symbol parameter min max t mck mclk cycle time 12.8 t mckl mclk low time 2.8 t mckh mclk high time 4.7 t ws nwait setup to mclkr 2.1 t wh nwait hold from ckf 1.3 t ale address latch open 2.4 t aleh address latch hold time 1.5 t ald address latch time 1.5 t addr mclkr to address valid 5.8 t ah address hold time from mclkr 3.8 t abe address bus enable time 2.5 t abz address bus disable time 2.5 t aph ape hold time from mclkr 1.3
20 CW001007 arm7tdmi microprocessor core t aps ape setup time to mclkf 2.8 t ape mclkf to address valid 3.9 t apeh address group hold time from mclkf 3.1 t dout mclkf to d[31:0] valid 7.6 t doh d[31:0] out hold from mclkf 0.9 t dis d[31:0] in setup time to mclkf 1.7 t dih d[31:0] in hold time from mclkf 1.7 t doutu mclkf to dout[31:0] valid 8.1 t dohu dout[31:0] hold time from mclkf 5.0 t disu din[31:0] setup time to mclkf 2.0 t dihu din hold time to mclkf 2.0 t nen mclkf to nenout valid 4.1 t nenh nenout hold time from mclkf 3.6 t bylh bl[3:0] hold time from mclkf 1.3 t byls bl[3:0] setup to from mclkr 0 t dbe data bus enable time from dber 5.1 t dbz data bus disable time from dbef 5.1 t dbnen dbe to nenout valid 1.3 t tbz address and data bus disable time from tbef 2.7 t tbe address and data bus enable time from tber 2.7 t rwd mclkr to nrw valid 4.7 t rwh nrw hold time from mclkr 4.0 t msd mclkf to nmreq & seq valid 10.6 t msh nmreq and seq hold time from mclkf 3.4 t bld mclkr to mas[1:0] and lock 7.0 table 3 ac parameters - tj = 125 c, 2.5 v (cont.) symbol parameter min max
CW001007 arm7tdmi microprocessor core 21 t blh mas[1:0] and lock hold from mclkr 4.0 t mdd mclkr to ntrans, nm[4:0], and tbit valid 5.8 t mdh ntrans and nm[4:0] hold time from mclkr 3.6 t opcd mclkr to nopc valid 6.2 t opch nopc hold time from mclkr 4.1 t cps cpa, cpb setup to mclkr 0 t cph cpa,cpb hold time from mclkr 1.6 t cpms cpa, cpb to nmreq, seq 6.9 t cpi mclkf to ncpi valid 6.1 t cpih ncpi hold time from mclkf 3.4 t cts con?g setup time 0 t cth con?g hold time 1.5 t abts abort setup time to mclkf 1.2 t abth abort hold time from mclkf 1.2 t is asynchronous interrupt setup time to mclkf for guaranteed recognition (isync = 0) 0.1 t im asynchronous interrupt guaranteed nonrecognition time (isync = 0) 1.4 t sis synchronous nfiq, nirq setup to mclkf (isync = 1) 0.1 t sih synchronous nfiq, nirq hold from mclkf (isync = 1) 1.4 t rs reset setup time to mclkr for guaranteed recognition 0 t rm reset guaranteed nonrecognition time 0.8 t exd mclkf to nexec valid 6.3 t exh nexec hold time from mclkf 3.7 t brks setup time of breakpt to mclkr 0 t brkh hold time of breakpt from mclkr 1.7 table 3 ac parameters - tj = 125 c, 2.5 v (cont.) symbol parameter min max
22 CW001007 arm7tdmi microprocessor core t bcems breakpt to ncpi, nexec, nmreq, seq delay 7.1 t dbgd mclkr to dbgack valid 8.2 t dbgh dgback hold time from mclkr 3.7 t rqs dbgrq setup time to mclkr for guaranteed recognition 1.1 t rqh dbgrq guaranteed nonrecognition time 0 t cdel mclk to eclk delay 0.7 t ctdel tck to eclk delay 1.0 t exts extern[1:0] setup time to mclkf 0 t exth extern[1:0] hold time from mclkf 1.2 t rg mclkf to rangeout0, rangeout1 valid 4.8 t rgh rangeout0, rangeout1 hold time from mclkf 3.1 t dbgrq dbgrq to dbgrqi valid 1.1 t rstd nresetf to d[], dbgack, ncpi, nenout, nexec, nmreq, seq valid 6.2 t commd mclkr to commrx, commtx valid 1.9 t trstd ntrstf to every output valid 7.6 t rstl nreset low for guaranteed reset 2 mclk cycles table 3 ac parameters - tj = 125 c, 2.5 v (cont.) symbol parameter min max
CW001007 arm7tdmi microprocessor core 23 table 4 ac parameters - tj = 125 c, 1.8 v symbol parameter min max t mck mclk cycle time 20.8 t mckl mclk low time 6.9 t mckh mclk high time 7.1 t ws nwait setup to mclkr 3.0 t wh nwait hold from ckf 1.8 t ale address latch open 3.4 t aleh address latch hold time 2.3 t ald address latch time 2.3 t addr mclkr to address valid 11.8 t ah address hold time from mclkr 5.7 t abe address bus enable time 3.7 t abz address bus disable time 3.8 t aph ape hold time from mclkr 1.9 t aps ape setup time to mclkf 4.2 t ape mclkf to address valid 6.0 t apeh address group hold time from mclkf 4.7 t dout mclkf to d[31:0] valid 11.6 t doh d[31:0] out hold from mclkf 1.4 t dis d[31:0] in setup time to mclkf 1.8 t dih d[31:0] in hold time from mclkf 2.5 t doutu mclkf to dout[31:0] valid 12.1 t dohu dout[31:0] hold time from mclkf 7.5 t disu din[31:0] setup time to mclkf 2.7 t dihu din[hold time to mclkf 2.9 t nen mclkf to nenout valid 6.2
24 CW001007 arm7tdmi microprocessor core t nenh nenout hold time from mclkf 5.4 t bylh bl[3:0] hold time from mclkf 1.8 t byls bl[3:0] setup to from mclkr 0 t dbe data bus enable time from dber 7.5 t dbz data bus disable time from dbef 7.4 t dbnen dbe to nenout valid 2.0 t tbz address and data bus disable time from tbef 3.7 t tbe address and data bus enable time from tber 3.9 t rwd mclkr to nrw valid 10.1 t rwh nrw hold time from mclkr 6.1 t msd mclkf to nmreq and seq valid 16.2 t msh nmreq and seq hold time from mclkf 5.0 t bld mclkr to mas[1:0] and lock 12.6 t blh mas[1:0] and lock hold from mclkr 5.9 t mdd mclkr to ntrans, nm[4:0], and tbit valid 11.8 t mdh ntrans and nm[4:0] hold time from mclkr 5.3 t opcd mclkr to nopc valid 12.5 t opch nopc hold time from mclkr 6.3 t cps cpa, cpb setup to mclkr 0 t cph cpa,cpb hold time from mclkr 2.2 t cpms cpa, cpb to nmreq, seq 10.5 t cpi mclkf to ncpi valid 9.3 t cpih ncpi hold time from mclkf 5.1 t cts con?g setup time 0 t cth con?g hold time 2.1 table 4 ac parameters - tj = 125 c, 1.8 v (cont.) symbol parameter min max
CW001007 arm7tdmi microprocessor core 25 t abts abort setup time to mclkf 1.8 t abth abort hold time from mclkf 1.7 t is asynchronous interrupt setup time to mclkf for guaranteed recognition (isync = 0) 0.3 t im asynchronous interrupt guaranteed nonrecognition time (isync = 0) 2.0 t sis synchronous nfiq, nirq setup to mclkf (isync = 1) 0.3 t sih synchronous nfiq, nirq hold from mclkf (isync = 1) 2.0 t rs reset setup time to mclkr for guaranteed recognition 0 t rm reset guaranteed nonrecognition time 1.2 t exd mclkf to nexec valid 9.6 t exh nexec hold time from mclkf 5.4 t brks setup time of breakpt to mclkr 0 t brkh hold time of breakpt from mclkr 2.5 t bcems breakpt to ncpi, nexec, nmreq, seq delay 10.7 t dbgd mclkr to dbgack valid 12.0 t dbgh dgback hold time from mclkr 5.5 t rqs dbgrq setup time to mclkr for guaranteed recognition 1.7 t rqh dbgrq guaranteed nonrecognition time 0 t cdel mclk to eclk delay 1.1 t ctdel tck to eclk delay 1.5 t exts extern[1:0] setup time to mclkf 0 t exth extern[1:0] hold time from mclkf 1.7 t rg mclkf to rangeout0, rangeout1 valid 7.4 table 4 ac parameters - tj = 125 c, 1.8 v (cont.) symbol parameter min max
26 CW001007 arm7tdmi microprocessor core t rgh rangeout0, rangeout1 hold time from mclkf 4.6 t dbgrq dbgrq to dbgrqi valid 1.7 t rstd nresetf to d[], dbgack, ncpi, nenout, nexec, nmreq, seq valid 8.1 t commd mclkr to commrx, commtx valid 2.9 t trstd ntrstf to every output valid 13.6 t rstl nreset low for guaranteed reset 2 mclk cycles table 4 ac parameters - tj = 125 c, 1.8 v (cont.) symbol parameter min max
CW001007 arm7tdmi microprocessor core 27 timing diagrams figure 5 general timing note: nwait, ape, ale and abe are all high during the cycle shown. t odel is the delay (on either edge) from mclk changing to eclk changing. mclk eclk a[31:0] nrw mas[1:0] lock nm[4:0], ntrans, tbit nopc nmreq, seq nexec t cdel t cdel t ah t addr t rwh t rwd t blh t bld t mdh t mdd t opch t opcd t msh t msd t exh t exd
28 CW001007 arm7tdmi microprocessor core figure 6 ale address control figure 7 ape address control figure 8 abe address control (ape high) 1. t ald is the time by which ale must be driven low in order to latch the current address in phase 2. if ale is driven low after t ald , then a new address will be latched. mclk ale a[31:0], nrw, lock, nopc, ntrans, mas[1:0] t ald t ale t ape t aps t aph mclk ape a[31:0], nrw, lock, nopc, ntrans, mas[1:0] mclk abe a[31:0], nrw, lock, nopc, ntrans, mas[1:0] t abz t abe t addr
CW001007 arm7tdmi microprocessor core 29 figure 9 bidirectional data write cycle figure 10 bidirectional data read cycle 1. dbe is high and nenin is low during the cycle shown. t nen t dout t nenh t doh mclk nenout d[31:0] 1. dbe is high and nenin is low during the cycle shown. t nen t bylh tbyls t dih t dis mclk nenout d[31:0] bl[3:0]
30 CW001007 arm7tdmi microprocessor core figure 11 data bus control figure 12 output 3-state time 1. the cycle shown is a data write cycle since nenout was driven low during phase. 2. here, dbe has ?rst been used to modify the behavior of the data bus, and then nenin. t dbnen t dbz t dbe t dout t doh t dbe t dbz t dbnen mclk nenout dbe d[31:0] nenin t tbe t tbz mclk tbe a[31:0] d[31:0] nrw, lock, nopc, ntrans, mas[1:0]
CW001007 arm7tdmi microprocessor core 31 figure 13 unidirectional data write cycle figure 14 unidirectional data read cycle figure 15 con?guration pin timing t nen t dohu t doutu mclk nenout dout[31:0] mclk nenout din[31:0] bl[3:0] t nen t disu t dihu t bylh t byls mclk bigend isync t cth t cts t cts t cth
32 CW001007 arm7tdmi microprocessor core figure 16 coprocessor timing figure 17 exception timing 1. normally, nmreq and seq become valid t msd after the falling edge of mclk. in this cycle the arm has been busy-waiting, waiting for a coprocessor to complete the instruction. if cpa and cpb change during phase 1, the timing of nmreq and seq will depend on t cpms . most systems should be able to generate cpa and cpb during the previous phase 2, and so the timing of nmreq and seq will always be t msd . mclk ncpi cpa, cpb nmreq, seq tcpi tcpih t cps t cph t cpms 1. t is /t rs guarantee recognition of the interrupt (or reset) source by the corresponding clock edge. t im /t rm guarantee nonrecognition by that clock edge. these inputs may be applied fully asyn- chronously where the exact cycle of recognition is unimportant. mclk abort nfiq, nirq nreset t abts t abth t is t im t rs t rm
CW001007 arm7tdmi microprocessor core 33 figure 18 debug timing figure 19 breakpoint timing figure 20 tck-eclk relationship mclk dbgack breakpt dbgrq extern[1:0] t dbgh t dbgd t brks t brkh t rqs t rqh t exts t exth 1. breakpt changing in the low phase of mclk to signal a watchpointed store can affect ncpi, nexec, nmreq, and seq in the low phase of mclk. mclk breakpt ncpi, nexec, nmreq, seq t bcems tck eclk t ctdel t ctdel
34 CW001007 arm7tdmi microprocessor core figure 21 mclk timing absolute maximum ratings table 5 lists the absolute maximum ratings for the g11 technology. exceeding these values may permanently damage the device. operating the device at absolute maximum ratings for extended periods may affect device reliability. 1. the arm7tdmi core is not clocked by the high phase of mclk enveloped by nwait. thus, during the cycles shown, nmreq and seq change once, during the ?rst low phase of mclk, and a[31:0] change once, during the second high phase of mclk. t addr t msd t ws t mckl t mckh t wh mclk nwait eclk nmreq, seq a[31:0] table 5 absolute maximum ratings (referenced to vss) symbol parameter min max units v dd supply voltage - 0.3 3.1 v v in input voltage applied to any pin - 1.0 vdd + 0.3 v t s storage temperature - 40 125 c
CW001007 arm7tdmi microprocessor core 35 dc operating conditions table 6 de?nes the recommended operating supply voltage and temperature for the g11-p technology. 1. voltages measured with respect to vss. 2. ic cmos-level inputs. table 7 de?nes the recommended operating supply voltage and temperature for the g11-v technology. 1. voltages measured with respect to vss. 2. ic cmos-level inputs. table 6 g11-p recommended operation conditions symbol parameter min typ max units notes v dd supply voltage 2.25 2.5 2.75 v v ihc ic input high voltage 2.0 vdd + 0.3 v 1,2 v ilc ic input low voltage vss - 0.5 0.8 v 1,2 t j operating junction temperature 0 +115 c table 7 g11-v recommended operation conditions symbol parameter min typ max units notes v dd supply voltage 1.62 1.8 1.98 v v ihc ic input high voltage 1.05 vdd + 0.3 v 1,2 v ilc ic input low voltage vss - 0.5 0.7 v 1,2 t j operating junction temperature 0 +115 c
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